Nanometric Electronics

 

This course aims to present design methodologies for nanometric scaled electronics, beyond Moore's Law, to connect People and Objects. It is based on the one hand on live stream lessons and on the other hand on application exercises. Graduate school courses are available for the students of Université Paris-Saclay. We will endeavor to determine the best performance compromise to offer the best electronic circuit to our client. We will be interested in Cadence, weak inversion, pink noise, and discreate time.

At the end of the course, you will be able to:

  • Say that the quadratic law is partially valid
  • Design circuits with a simple proportion
  • Justify your choice with quantum physics.

Course Outline:

Course 1 :  Low-power high-performance electronics: modeling and physical design

                   2020_NanoElec Course 1 (PMF)

Course 2:  𝑔𝑚/𝐼𝐷 design methodology: Single-stage amplifier

                   2020_NanoElec Course 2 (PMF)

Exercise 1:  Design of Single-stage amplifier topologies(practical exercises)

                  2020_NanoElec TD 1.pdf (PMF)

Course 3:  Low power high performance amplifiers: OTA Miller, folded cascode

                  2020_NanoElec Course 3.pdf (PMF)

Exercise 2:  Design of two-stage amplifier topologies (practical exercises)

                  2020_NanoElec TD 2.pdf (PMF)

Lab Activity:  OTA Design of Experiments using Virtuoso CADENCE

Course 4:  Discrete-time Analog Devices: Comparators, S/H, TG

                  2020_NanoElec Course 4.pdf (PMF)

Exercise 3:  Design of discrete-time devices (practical exercises)

                  2020_NanoElec TD 3.pdf (PMF)

Course 5:  Low power high performance analog architectures: Gm-C filters, gyrators, delay lines

                  2020_NanoElec Course 5.pdf (EAM)

Exercise 4:  Analog architectures (practical examples

                  2020_NanoElec TD4.pdf (EAM)

Course 6:  Frequency synthesizer: theory

                  2020_NanoElec Course 6.pdf (EAM)

Exercise 5:  Frequency synthesizer: design example

                  2020_NanoElec TD 5.pdf (EAM)

Course 7:  Low noise electronics: models and sources

                  2020_NanoElec Course 7.pdf (PMF)

Exercise 6:  Low Noise Amplifier Design 

                  2020_NanoElec TD 6.pdf (PMF)

Graded Homework

  • Begins on November 30, 2021 and ends on January 20, 2022 at 6 p.m.
  • Includes 3 hours of Lab work on January 14, 2022 from 1:45 p.m. to 5 p.m.
  • Consists of two parts: system design (1/3 of the grade) and transistor design (2/3 of the grade)
  • Must be returned in the form firstname_name.pdf or firstname_name.zip by email.
  • Questions are available at 2021 NanoElec exam 2v0.pdf
  • Custom design specifications at Design Specification Student.pdf

Bibliography

  1. Jespers, P. (2010). The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits. In Springer US. Springer US. https://doi.org/10.1007/978-0-387-47101-3
  2. Carusone, T. C., Johns, D. A., & Martin, K. W. (2012). Analog Integrated Circuit Design (2nd ed.). John Wiley & Sons, Inc.
  3. Debroux, J.-F. (2020). Analog IC Designer’s Handbook. Online available at PDF